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ECE-271
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VerilogCPU
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81c9baade202b902c226e9987e7aca2adc64aa63
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Danila Fedorin
81c9baade2
Add the CPU controller.
2018-06-05 22:57:01 -07:00
tasm
Add an assembly program to demonstrate reading.
2018-06-05 17:36:18 -07:00
alu.sv
Initial commit. Working CPU!
2018-06-05 00:06:45 -07:00
assembler.cr
Add help to assembler.
2018-06-05 17:28:24 -07:00
cpu_controller.sv
Add the CPU controller.
2018-06-05 22:57:01 -07:00
cpu.sv
Fix a port width problem, and change file permissions.
2018-06-05 22:56:46 -07:00
edge_detector.sv
Add the CPU controller.
2018-06-05 22:57:01 -07:00
memory.sv
Fix a port width problem, and change file permissions.
2018-06-05 22:56:46 -07:00
mux2.sv
Fix a port width problem, and change file permissions.
2018-06-05 22:56:46 -07:00
mux4.sv
Fix a port width problem, and change file permissions.
2018-06-05 22:56:46 -07:00
register.sv
Fix a port width problem, and change file permissions.
2018-06-05 22:56:46 -07:00
spi_slave.sv
Add the CPU controller.
2018-06-05 22:57:01 -07:00
Description
A CPU written in SystemVerilog for ECE 271.
212
KiB
Languages
SystemVerilog
51.8%
Crystal
48.2%
