Update code with new edge detector.

cpu_controller.sv

@@ -25,7 +25,8 @@ module cpu_controller(input logic clk, reset,
 	edge_detector inst_ready_detector(
 		.in(inst_ready),
 		.clk(clk),
-		.out(inst_ready_edge));
+		.reset(reset),
+		.pos_edge(inst_ready_edge));
 
 	logic prog_forward_clk;
 

edge_detector.sv

@@ -3,12 +3,16 @@
  * and produces an output of 1 when the signal changes from 0 to 1.
  * Otherwise, the output is 0.
  */
-module edge_detector(input logic in, clk,
-					 output logic out);
+momodule edge_detector(input logic in, clk, reset,
+		     output logic pos_edge, neg_edge);
 	logic old_in;
 
 	always_ff@(posedge clk)
-		old_in <= in;
+		if(reset)
+			old_in <= 0;
+		else
+			old_in <= in;
 
-	assign out = in & ~old_in;
-endmodule
+	assign pos_edge = in & ~old_in;
+	assign neg_edge = ~in & old_in;
+endmodulemodule

spi_slave.sv

@@ -17,17 +17,21 @@ module spi_slave #(width=32)
 				   output logic [width-1:0] data);
 	logic [width-1:0] storage;
 	logic unsigned [$clog2(width)-1:0] counter;
-	logic old_clk;
+	logic clk_edge;
+	edge_detector clk_detector(
+		.in(master_clk),
+		.clk(clk),
+		.reset(reset),
+		.pos_edge(clk_edge));
 
 	always_ff@(posedge clk)
 		if(reset) begin
 			counter <= 0;
-			old_clk <= 0;
 			storage <= 0;
 			done <= 0;
 			ready <= 0;
 		end else begin
-			if (~ss & master_clk & ~old_clk) begin
+			if (~ss & clk_edge) begin
 				storage <= storage << 1 | mosi;
 				if (counter == width - 1) begin
 					ready <= 1;
@@ -39,7 +43,6 @@ module spi_slave #(width=32)
 					counter <= counter + 1;
 				end
 			end
-			old_clk <= master_clk;
 		end
 
 	assign data = storage;