Update code with new edge detector.

edge_detector.sv

@@ -3,12 +3,16 @@
  * and produces an output of 1 when the signal changes from 0 to 1.
  * Otherwise, the output is 0.
  */
-module edge_detector(input logic in, clk,
-					 output logic out);
+momodule edge_detector(input logic in, clk, reset,
+		     output logic pos_edge, neg_edge);
 	logic old_in;
 
 	always_ff@(posedge clk)
-		old_in <= in;
+		if(reset)
+			old_in <= 0;
+		else
+			old_in <= in;
 
-	assign out = in & ~old_in;
-endmodule
+	assign pos_edge = in & ~old_in;
+	assign neg_edge = ~in & old_in;
+endmodulemodule