Add comments.

alu.sv

@@ -1,3 +1,19 @@
+/**
+ * Arithmetic Logic Unit, as described in our book. This is a general
+ * purpose aritmetic circuit. The width parameter specifies the operand width,
+ * and left and right are the operands. op is the instruction, which decodes as
+ * follows:
+ 
+ * 000 left AND right
+ * 001 left OR right
+ * 010 left + right
+ * 011 unused
+ * 000 left AND NOT right
+ * 001 left OR NOT right
+ * 010 left - right
+ * 011 SLT left, right
+ *
+ */
 module alu #(width=32)
 			 (input logic [width-1:0] left, right,
 			  input logic [2:0] op,
@@ -9,13 +25,13 @@ module alu #(width=32)
 		.right(not_right),
 		.select(op[2]),
 		.out(selected_right));
-		
+
 	logic [width-1:0] op_and, op_or, op_sum, op_slt;
 	assign op_and = left & selected_right;
 	assign op_or = left | selected_right;
 	assign op_sum = left + selected_right + op[2];
 	assign op_slt = op_sum[width-1];
-	
+
 	mux4 output_mux(
 		.first(op_and),
 		.second(op_or),
@@ -23,4 +39,4 @@ module alu #(width=32)
 		.fourth(op_slt),
 		.select(op[1:0]),
 		.out(out));
-endmodule
+endmodule