ECE-271/VerilogCPU
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity
10 Commits 1 Branch 0 Tags
672eae920a6768e41605f20d243b114c2995d3e9
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Danila Fedorin 672eae920a Add comments.
2018-06-05 23:42:20 -07:00
tasm
Add an assembly program to demonstrate reading.
2018-06-05 17:36:18 -07:00
alu.sv
Add comments.
2018-06-05 23:42:20 -07:00
assembler.cr
Add help to assembler.
2018-06-05 17:28:24 -07:00
cpu_controller.sv
Add comments.
2018-06-05 23:42:20 -07:00
cpu.sv
Add comments.
2018-06-05 23:42:20 -07:00
edge_detector.sv
Add comments.
2018-06-05 23:42:20 -07:00
memory.sv
Add comments.
2018-06-05 23:42:20 -07:00
mux2.sv
Add comments.
2018-06-05 23:42:20 -07:00
mux4.sv
Add comments.
2018-06-05 23:42:20 -07:00
register.sv
Add comments.
2018-06-05 23:42:20 -07:00
spi_encoder.cr
Add script to generate SPI DO files.
2018-06-05 23:01:13 -07:00
spi_slave.sv
Add comments.
2018-06-05 23:42:20 -07:00
Description
A CPU written in SystemVerilog for ECE 271.
212 KiB
Languages
SystemVerilog 51.8%
Crystal 48.2%