Add comments.

register.sv

@@ -1,10 +1,16 @@
+/**
+ * Register file as used by the CPU. Has two read addresses so that
+ * two-register instructions can be performed in one cycle. Just like memory,
+ * reading is asynchronous, while writes occur on positive clock edge.
+ * wen, waddr, and in are used to write to register memory.
+ */
 module registers #(width=32)
 				   (input logic [2:0] raddr1, raddr2, waddr,
 				    input clk, wen, reset,
 					input logic [width-1:0] in,
 					output logic [width-1:0] out1, out2);
 	logic [width-1:0] data [0:7];
-				
+
 	always_ff@(posedge clk)
 		if (reset) begin
 			data <= '{default: 0};
@@ -14,5 +20,5 @@ module registers #(width=32)
 
 	assign out1 = data[raddr1];
 	assign out2 = data[raddr2];
-	
-endmodule
+
+endmodule