Initial commit. Working CPU!

alu.sv

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+module alu #(width=32)
+			 (input logic [width-1:0] left, right,
+			  input logic [2:0] op,
+			  output logic [width-1:0] out);
+	logic [width-1:0] selected_right, not_right;
+	assign not_right = ~right;
+	mux2 #(width) right_mux(
+		.left(right),
+		.right(not_right),
+		.select(op[2]),
+		.out(selected_right));
+		
+	logic [width-1:0] op_and, op_or, op_sum, op_slt;
+	assign op_and = left & selected_right;
+	assign op_or = left | selected_right;
+	assign op_sum = left + selected_right + op[2];
+	assign op_slt = op_sum[width-1];
+	
+	mux4 output_mux(
+		.first(op_and),
+		.second(op_or),
+		.third(op_sum),
+		.fourth(op_slt),
+		.select(op[1:0]),
+		.out(out));
+endmodule