ECE-271/VerilogCPU
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6bceee5e68e4f55949dcfbd1ebf5a138c50a9e07
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Danila Fedorin 6bceee5e68 Initial commit. Working CPU!
2018-06-05 00:06:45 -07:00
alu.sv
Initial commit. Working CPU!
2018-06-05 00:06:45 -07:00
cpu.sv
Initial commit. Working CPU!
2018-06-05 00:06:45 -07:00
memory.sv
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2018-06-05 00:06:45 -07:00
mux2.sv
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2018-06-05 00:06:45 -07:00
mux4.sv
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2018-06-05 00:06:45 -07:00
register.sv
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2018-06-05 00:06:45 -07:00
Description
A CPU written in SystemVerilog for ECE 271.
212 KiB
Languages
SystemVerilog 51.8%
Crystal 48.2%