Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00
commit 6bceee5e68
6 changed files with 178 additions and 0 deletions
--- a/mux2.sv
+++ b/mux2.sv
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+module mux2 #(width=32)
+			 (input logic [width-1:0] left, right,
+			  input logic select,
+			  output logic [width-1:0] out);
+	assign out = select ? right : left;
+endmodule