Initial commit. Working CPU!

register.sv

@@ -0,0 +1,18 @@
+module registers #(width=32)
+				   (input logic [2:0] raddr1, raddr2, waddr,
+				    input clk, wen, reset,
+					input logic [width-1:0] in,
+					output logic [width-1:0] out1, out2);
+	logic [width-1:0] data [0:7];
+				
+	always_ff@(posedge clk)
+		if (reset) begin
+			data <= '{default: 0};
+		end else begin
+			if(wen) data[waddr] <= in;
+		end
+
+	assign out1 = data[raddr1];
+	assign out2 = data[raddr2];
+	
+endmodule