ECE-271/VerilogCPU
1
0
Fork 0
Code Issues 2 Pull Requests Releases Wiki Activity

Add inputs and an instruction to read from them.

Browse Source
This commit is contained in:
Danila Fedorin 2018-06-05 18:58:46 -07:00
parent c0862e34ba
commit d183a7e1de
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
cpu.sv
View File

@ -1,5 +1,6 @@
module cpu (input logic clk, reset, module cpu (input logic clk, reset,
input logic prog, input logic prog,
input logic [15:0] inputs,
input logic[31:0] pinst, input logic[31:0] pinst,
input logic[7:0] paddr, input logic[7:0] paddr,
output logic [31:0] disp); output logic [31:0] disp);
@ -12,7 +13,7 @@ module cpu (input logic clk, reset,
logic [15:0] const_val; logic [15:0] const_val;
logic [31:0] const_extend; logic [31:0] const_extend;
logic [31:0] cpu_disp; logic [31:0] cpu_disp;
logic [31:0] reg_alu_out, const_alu_out; logic [31:0] reg_alu_out, const_alu_out, val_out;
logic should_jump, should_write, use_const; logic should_jump, should_write, use_const;
assign op = inst[31:26]; assign op = inst[31:26];
@ -63,6 +64,12 @@ module cpu (input logic clk, reset,
.left(reg_alu_out), .left(reg_alu_out),
.right(const_alu_out), .right(const_alu_out),
.select(use_const), .select(use_const),
.out(val_out));
mux2 #(32) rd_mux(
.left(val_out),
.right({16'b0, inputs}),
.select(~inst[28] & inst[27] & inst[26]),
.out(rd_val)); .out(rd_val));
assign pc_compute = rt_val + const_val; assign pc_compute = rt_val + const_val;