Danila Fedorin d183a7e1de Add inputs and an instruction to read from them.

2018-06-05 18:58:46 -07:00

tasm

Add an assembly program to demonstrate reading.

2018-06-05 17:36:18 -07:00

alu.sv

Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00

assembler.cr

Add help to assembler.

2018-06-05 17:28:24 -07:00

cpu.sv

Add inputs and an instruction to read from them.

2018-06-05 18:58:46 -07:00

memory.sv

Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00

mux2.sv

Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00

mux4.sv

Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00

register.sv

Initial commit. Working CPU!

2018-06-05 00:06:45 -07:00

Description

A CPU written in SystemVerilog for ECE 271.

212 KiB

Languages

SystemVerilog 51.8%

Crystal 48.2%