A CPU written in SystemVerilog for ECE 271.
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/**
* Simple edge detector circuit. Takes in a clock and a signal,
* and produces an output of 1 when the signal changes from 0 to 1.
* Otherwise, the output is 0.
*/
momodule edge_detector(input logic in, clk, reset,
output logic pos_edge, neg_edge);
logic old_in;
always_ff@(posedge clk)
if(reset)
old_in <= 0;
else
old_in <= in;
assign pos_edge = in & ~old_in;
assign neg_edge = ~in & old_in;
endmodulemodule