51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
/**
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* Specialized SPI slave.
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* Reads width bits at a time, and sets the ready flag
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* whenever a full 32 bits has been read. Also, recognizes
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* 0x00 as a pattern, and when full 0s are read, sets the done flag.
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* 0x00 is a special value in the CPU programming process that indicates
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* end-of-program.
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*
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* master_clk, ss, and mosi are all SPI-specific inputs.
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* data should only be read when ready is high.
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*/
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module spi_slave #(width=32)
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(input logic clk, reset,
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input logic master_clk, ss, mosi,
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output logic ready,
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output logic done,
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output logic [width-1:0] data);
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logic [width-1:0] storage;
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logic unsigned [$clog2(width)-1:0] counter;
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logic clk_edge;
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edge_detector clk_detector(
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.in(master_clk),
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.clk(clk),
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.reset(reset),
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.pos_edge(clk_edge));
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always_ff@(posedge clk)
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if(reset) begin
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counter <= 0;
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storage <= 0;
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done <= 0;
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ready <= 0;
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end else begin
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if (~ss & clk_edge) begin
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storage <= storage << 1 | mosi;
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if (counter == width - 1) begin
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ready <= 1;
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done <= ~(|storage);
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counter <= 0;
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end else begin
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done <= 0;
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ready <= 0;
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counter <= counter + 1;
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end
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end
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end
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assign data = storage;
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endmodule
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