89 lines
1.8 KiB
Systemverilog
89 lines
1.8 KiB
Systemverilog
module cpu (input logic clk, reset,
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input logic prog,
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input logic[31:0] pinst,
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input logic[7:0] paddr,
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output logic [31:0] disp);
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logic [7:0] pc;
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logic [7:0] pc_next, pc_compute;
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logic [31:0] inst;
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logic [5:0] op;
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logic [2:0] rd, rs, rt;
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logic [31:0] rd_val, rs_val, rt_val;
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logic [15:0] const_val;
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logic [31:0] const_extend;
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logic [31:0] cpu_disp;
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logic [31:0] reg_alu_out, const_alu_out;
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logic should_jump, should_write, use_const;
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assign op = inst[31:26];
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assign rd = inst[25:23];
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assign rs = inst[22:20];
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assign rt = inst[19:17];
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assign const_val = inst[15:0];
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assign should_write = inst[31];
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assign use_const = inst[30];
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assign should_jump = inst[29];
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assign const_extend = const_val;
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registers #(32) regs(
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.raddr1(rs),
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.raddr2(rt),
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.waddr(rd),
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.in(rd_val),
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.wen(should_write),
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.clk(clk),
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.reset(reset),
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.out1(rs_val),
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.out2(rt_val));
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memory #(32) insts(
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.raddr(pc),
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.waddr(paddr),
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.wen(prog),
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.in(pinst),
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.clk(clk),
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.out(inst),
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.reset(reset));
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alu #(32) reg_alu(
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.left(rs_val),
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.right(rt_val),
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.op(inst[28:26]),
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.out(reg_alu_out));
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alu #(32) const_alu(
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.left(rs_val),
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.right(const_extend),
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.op(inst[28:26]),
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.out(const_alu_out));
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mux2 #(32) out_mux(
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.left(reg_alu_out),
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.right(const_alu_out),
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.select(use_const),
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.out(rd_val));
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assign pc_compute = rt_val + const_val;
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mux2 #(8) pc_mux(
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.left(pc + 1),
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.right(pc_compute),
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.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
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.out(pc_next));
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always_ff@(posedge clk)
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if(reset) begin
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pc <= 0;
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cpu_disp <= 0;
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end else if(!prog) begin
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case(op)
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6'b0000000: cpu_disp <= rs_val;
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endcase
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pc <= pc_next;
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end
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assign disp = cpu_disp;
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endmodule |