24 lines
653 B
Systemverilog
24 lines
653 B
Systemverilog
/**
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* CPU-specific memory. raddr is used for reading,
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* while wen (write enable), waddr, and in are used in combination to write.
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* Reads are performed immediately, but writes are performed on
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* positive clock edge. Reset clears the memory to 0.
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*/
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module memory #(width=32)
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(input logic [7:0] raddr, waddr,
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input logic [width-1:0] in,
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input logic clk, wen, reset,
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output logic [width-1:0] out);
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logic [width-1:0] data [0:255];
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always_ff@(posedge clk)
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if(reset) begin
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data <= '{default: 0};
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end else begin
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if(wen) begin
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data[waddr] <= in;
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end
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end
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assign out = data[raddr];
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endmodule
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