28 lines
524 B
Systemverilog
28 lines
524 B
Systemverilog
/**
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* A four-input multiplexer.
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*/
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module mux4 #(width=32)
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(input logic [width-1:0] first, second, third, fourth,
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input logic [1:0] select,
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output logic [width-1:0] out);
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logic [width-1:0] lower, upper;
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mux2 lower_mux(
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.left(first),
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.right(second),
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.select(select[0]),
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.out(lower));
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mux2 upper_mux(
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.left(third),
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.right(fourth),
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.select(select[0]),
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.out(upper));
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mux2 final_mux(
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.left(lower),
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.right(upper),
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.select(select[1]),
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.out(out));
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endmodule
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