**Danila Fedorin**8 months ago

**7 changed files**with

**178 additions**and

**1 deletions**

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`\documentclass{article}` |
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`\usepackage[margin=1in]{geometry}` |
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`\usepackage{graphicx}` |
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`\title{Homework 2}` |
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`\begin{document}` |
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`\maketitle` |
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`\section*{Q1}` |
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`The current scales linearly with oxide capacitance per unit area, $C_{ox}$.` |
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`Doubling the thickness of the insulator is akin to doubling the distance between the two plates,` |
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`which halves $C_{ox}$. Thus, current would be halved as well.` |
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```
``` |
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`\section*{Q2}` |
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`This occurs, by definition, at the threshold voltage, $V_t$.` |
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```
``` |
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`\section*{Q3}` |
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`\begin{figure}[h]` |
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` \centering` |
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` \includegraphics[width=0.8\linewidth]{Q3.png}` |
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` \label{fig:iv}` |
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` \caption{}` |
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`\end{figure}` |
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```
``` |
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`\section*{Q4}` |
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`The depletion region is larger because of the potential on the drain.` |
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`Since (for an NMOS transistor) the source is tied to the lowest potential, to drive current` |
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`through the transistor, we need to apply potential to the drain.` |
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`Doing so pushes more carriers into the depletion region, causing it to grow.` |
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```
``` |
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`\section*{Q5}` |
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`The potential is $V_{gs} - V_t$, which is also written as $V_{GT}$ in the book.` |
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```
``` |
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`\section*{Q6}` |
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`The transistor in the picture likely suffers from velocity saturation. I think` |
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`so because for each step in gate voltage, the current increases by the same amount.` |
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`However, our simple models predict that this should be a quadratic increase.` |
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`This difference in behavior is typically caused by velocity saturation.` |
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```
``` |
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`\section*{Q7}` |
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`The transistor in the picture likely suffers from impact ionization.` |
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`I think so because at high drain-source voltages, the current starts` |
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`to "bend upwards", increasing more than it is expected to past the saturation` |
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`point. This can be caused by "hot" electrons producing electron/hole pairs` |
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`on impact with the substrate atoms. These pairs serve as carriers, thereby` |
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`contributing to increased current.` |
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```
``` |
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`\end{document}` |

`@ -0,0 +1,121 @@` |
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`\documentclass{article}` |
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`\usepackage[margin=1in]{geometry}` |
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`\usepackage{graphicx}` |
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`\usepackage{amsmath}` |
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`\title{Homework 3}` |
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`\begin{document}` |
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`\maketitle` |
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`\section*{Q1}` |
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`Given the logical formula, we can follow` |
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`the following process to convert it into strictly` |
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`inverters, NOR, and NAND gates:` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` & \lnot((AB+C)D+E) \\` |
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` \Leftrightarrow & \lnot(\lnot\lnot(AB+C)D+E) & \text{(negation involutive)} \\` |
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` \Leftrightarrow & \lnot(\lnot(\lnot(AB+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\` |
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` \Leftrightarrow & \lnot(\lnot(\lnot(\lnot\lnot AB+C)+\lnot D)+E) & \text{(negation involutive)} \\` |
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` \Leftrightarrow & \lnot(\lnot(\lnot(\lnot(\lnot A + \lnot B)+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`This corresponds to the following circuit:` |
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```
``` |
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`\begin{figure}[h]` |
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` \centering` |
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` \includegraphics[width=0.7\linewidth]{Q1HW3.png}` |
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`\end{figure}` |
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```
``` |
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`\pagebreak` |
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`\section*{Q2}` |
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`Making Scott's adjustment (adding a top-level 'not' to the formula in the assignment) yields the following:` |
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```
``` |
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`\begin{figure}[h]` |
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` \centering` |
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` \includegraphics[width=0.7\linewidth]{Q2.png}` |
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`\end{figure}` |
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```
``` |
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`\pagebreak` |
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`\section*{Q3}` |
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`The book gives the following equation for determing the ideal number of stages:` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` N &= \log_{\rho}F \\` |
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` 0 &= p_\text{inv} + \rho(1-\ln\rho)` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`Where $p_\text{inv}$ is the intrinsic delay of an inverter.` |
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`For $p_\text{inv} = 5$, we have $\rho = 6.14$. We then compute $F$:` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` & F &= GBH \\` |
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` & G &= 1 \\` |
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` & B &= 1 \\` |
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` & H &= 1000 \\` |
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` \Rightarrow & F &= 1000` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`The ideal number of stages is then:` |
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```
``` |
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`\begin{equation*}` |
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` \log_\rho F = 3.8 \approx 4` |
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`\end{equation*}` |
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```
``` |
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`For all inverters, then, we get the following:` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` \hat{f} &= \sqrt[4]{1000} \\` |
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` \text{sz}_4 &= 1000/\hat{f}^1 = 178 \\` |
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` \text{sz}_3 &= 1000/\hat{f}^2 = 31.6 \\` |
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` \text{sz}_2 &= 1000/\hat{f}^3 = 5.62 \\` |
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` \text{sz}_1 &= 1000/\hat{f}^4 = 1 \\` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`\pagebreak` |
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`\section*{Q4}` |
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`First, to compute stage effort $\hat{f}$.` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` & F &= GBH \\` |
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` & G &= \left(\frac{4}{3}\right)\left(\frac{5}{3}\right)\left(\frac{5}{3}\right) \\` |
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` & B &= 3 \\` |
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` & H &= 1000 \\` |
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` \Rightarrow & F &= 11111` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`Assuimng a $p_\text{invs}$ of 1, and thus $\rho = 3.59$, we get:` |
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```
``` |
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`\begin{equation*}` |
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` \log_\rho F = 7.2 \approx 7` |
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`\end{equation*}` |
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```
``` |
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`Since we currently have 3 stages, we should insert 4 inverters.` |
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`It appears as though inserting inverters only at the end makes it` |
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`too difficult for the first-stage NAND gate to drive the 3-branched` |
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`NOR gates (we end up with an optimal size less than 1). Instead,` |
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`I will insert two inverters right after the NAND2 gate, and two more` |
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`inverters at the end. We can now compute gate sizes:` |
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```
``` |
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`\begin{equation*}` |
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` \begin{aligned}` |
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` \hat{f} &= \sqrt[7]{11111} \\` |
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` \text{sz}_7 &= 1000/\hat{f}^1 = 264 \\` |
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` \text{sz}_6 &= 1000/\hat{f}^2 = 69.8 \\` |
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` \text{sz}_5 &= 1000/\hat{f}^3 * \left(\frac{5}{3}\right) = 30.8 \\` |
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` \text{sz}_4 &= 1000/\hat{f}^4 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right) = 13.5 \\` |
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` \text{sz}_3 &= 1000/\hat{f}^5 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 10.7 \\` |
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` \text{sz}_2 &= 1000/\hat{f}^6 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 2.84 \\` |
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` \text{sz}_1 &= 1000/\hat{f}^7 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 1 \\` |
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` \end{aligned}` |
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`\end{equation*}` |
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```
``` |
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`\end{document}` |

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