2021-01-27 14:51:16 -08:00

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 \documentclass{article}  \usepackage[margin=1in]{geometry}  \usepackage{graphicx}  \title{Homework 2}  \begin{document}  \maketitle  \section*{Q1}  The current scales linearly with oxide capacitance per unit area, $C_{ox}$.  Doubling the thickness of the insulator is akin to doubling the distance between the two plates,  which halves $C_{ox}$. Thus, current would be halved as well.    \section*{Q2}  This occurs, by definition, at the threshold voltage, $V_t$.    \section*{Q3}  \begin{figure}[h]   \centering   \includegraphics[width=0.8\linewidth]{Q3.png}   \label{fig:iv}   \caption{}  \end{figure}    \section*{Q4}  The depletion region is larger because of the potential on the drain.  Since (for an NMOS transistor) the source is tied to the lowest potential, to drive current  through the transistor, we need to apply potential to the drain.  Doing so pushes more carriers into the depletion region, causing it to grow.    \section*{Q5}  The potential is $V_{gs} - V_t$, which is also written as $V_{GT}$ in the book.    \section*{Q6}  The transistor in the picture likely suffers from velocity saturation. I think  so because for each step in gate voltage, the current increases by the same amount.  However, our simple models predict that this should be a quadratic increase.  This difference in behavior is typically caused by velocity saturation.    \section*{Q7}  The transistor in the picture likely suffers from impact ionization.  I think so because at high drain-source voltages, the current starts  to "bend upwards", increasing more than it is expected to past the saturation  point. This can be caused by "hot" electrons producing electron/hole pairs  on impact with the substrate atoms. These pairs serve as carriers, thereby  contributing to increased current.    \end{document}