Labs/final/todo.md

* [x] Figure out the weird opAmp behavior
* [x] Design cell with strict metal policies
* [x] Add precharger version of memory cell (or explain how they compose)
* [x] Test cell in the _middle_.
* [x] Walk through the consequences of the read/write block being in the middle.
* [x] Figure out what to do with flopped write block.
* [x] Test data close to write block (it pulls up past clock low!)
* [ ] Drive wires to zero?
* [ ] Add missing well connection in layout
* [ ] Make sure width isn't too horrible
* [ ] Model additional delay for read read/write block select?
* [ ] Model worst case of decoder
* [ ] Cite [this](https://ieeexplore.ieee.org/document/210039)