Labs/final/todo.md

• Figure out the weird opAmp behavior
• Design cell with strict metal policies
• Add precharger version of memory cell (or explain how they compose)
• Test cell in the middle.
• Walk through the consequences of the read/write block being in the middle.
• Figure out what to do with flopped write block.
• Test data close to write block (it pulls up past clock low!)
• Drive wires to zero?
• Add missing well connection in layout
• Make sure width isn't too horrible
• Model additional delay for read read/write block select?
• Model worst case of decoder
• Cite this