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WIP (still buggy) 2ns design

This commit is contained in:
Danila Fedorin 2021-03-12 13:53:24 -08:00
parent 2010fcdf52
commit 5f8a49ab9a
2 changed files with 32 additions and 18 deletions
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32
final/SRAM_bits.cir
View File

@ -38,6 +38,13 @@ Xt lt rt wire len='len' wid='wid'
Xf lf rf wire len='len' wid='wid'
.ends
.subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10
Xt lt rt wire len='len' wid='wid'
Xf lf rf wire len='len' wid='wid'
Xpt rt clk vdd pp ww='ww'
Xpf rf clk vdd pp ww='ww'
.ends
.subckt nn d g s ww=100
mnfet d g s 0 nmos L=ll w='ww*ll'
.ends
@ -141,14 +148,15 @@ Xn1 ot1 in1 ot0 eva nnd3 size ='size'
.subckt write1 btt bff dii rwt clk
* TODO: sizes
Xclk clkb clk inv
Xdii diib dii inv
Xrwn dorw clkb rwt nor2
Xng pd dorw gnd nn ww='10'
Xngt btt dii pd nn ww='10'
Xngf bff diib pd nn ww='10'
Xpct btt dorw vdd pp ww='10'
Xpcf bff dorw vdd pp ww='10'
Xclk clkb clk inv size='25'
Xdii diib dii inv size='25'
Xrwn dorw clkb rwt nor2 size='50'
Xdt pdt dii gnd nn ww='50'
Xdf pdf diib gnd nn ww='50'
Xwt btt dorw pdt nn ww='50'
Xwf bff dorw pdf nn ww='50'
Xpct btt clk vdd pp ww='25'
Xpcf bff clk vdd pp ww='25'
.ends write1
@ -184,10 +192,10 @@ Xrst01 rst01 rst0 rst1 nnd2
Xrst23 rst23 rst2 rst3 nnd2
Xnset01 nset01 set01 inv
Xnset23 nset23 set23 inv
Xp01 dot nset01 vdd pp
Xp23 dot nset23 vdd pp
Xn01 dot rst01 gnd nn
Xn23 dot rst23 gnd nn
Xp01 nn1 nset01 vdd pp
Xp23 nn1 nset23 vdd pp
Xn01 nn1 rst01 gnd nn
Xn23 nn1 rst23 gnd nn
Xh1 dot nn1 inv
Xh2 nn1 dot inv
.ends readCollect

18
final/testBuffer.cir
View File

@ -21,9 +21,9 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel*****
.param per = 20ns
.param dataLead=500ps
.param lw=1000
.param per = 2ns
.param dataLead=per*0.1
.param lw=1800
.param wirew=12
vdd vdd 0 'supply'
@ -35,14 +35,20 @@ Xdii din dat1 period='per' start='per' total=4 duty=2
Xwr bt1 bf1 din rdw clk write1
Xw1 bt1 btt bf1 bff wire_dual len='lw' wid='wirew'
Xmd btt bff memLoad number =254
Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=16
Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'
Xmd2 bt3 bf3 memLoad number=16
Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff memLoad number =15
Xla btt bff clk mem1
Xrd btt bff set rst rdw clk readSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
.ic V(la:tt)=0 V(la:ff)=1
.ic V(bt2)=1
.tran 1p 'per*10'
.tran 1p 'per*20'