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1.24ns

This commit is contained in:
Danila Fedorin 2021-03-15 16:02:04 -07:00
parent c866f63e8c
commit 8ba9d02a8e
2 changed files with 10 additions and 10 deletions
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2
final/SRAM_bits.cir
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@ -190,7 +190,7 @@ Xh2 nn1 dot inv
.subckt readSub btt bff set rst rwt clk en .subckt readSub btt bff set rst rwt clk en
Xnd trigger rwt clk en nnd3 Xnd trigger rwt clk en nnd3
Xinv triggerb trigger inv size='40' Xinv triggerb trigger inv size='40'
Xamp set rst btt bff triggerb senseAmp size='200' Xamp set rst btt bff triggerb senseAmp size='80'
.ends read1 .ends read1
.subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3

18
final/testBuffer.cir
View File

@ -21,24 +21,24 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel***** *********begin: topLevel*****
.param per = 1.3ns .param per = 1.24ns
.param dataLead=per*0.1 .param dataLead=per*0.1
.param lw=1800 .param lw=2000
.param wirew=12 .param wirew=8
vdd vdd 0 'supply' vdd vdd 0 'supply'
Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50 Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=200
Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=100 Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=200
Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=100 Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=200
Xdii din dat1 period='per' start='per' total=4 duty=2 sz=100 Xdii din dat1 period='per*2' start='per' total=4 duty=1 sz=200
Xad adf ad clk flop Xad adf ad clk flop
Xdinff dinf din clk flop Xdinff dinf din clk flop
Xrdwff rdwf rdw clk flop Xrdwff rdwf rdw clk flop
Xdec choose adf clk decModel Xdec choose adf clk decModel
Xwr bt3 bf3 din rdw clk write1 Xwr bt3 bf3 din rdwf clk write1
Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew' Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=15 Xmd1 bt2 bf2 memLoad number=15
Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew' Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'
@ -48,7 +48,7 @@ Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff memLoad number =16 Xmd4 btt bff memLoad number =16
Xla bt1 bf1 choose mem1 Xla bt1 bf1 choose mem1
Xrd btt bff set rst rdw clk choose readSub Xrd btt bff set rst rdwf clk choose readSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
.ic V(la:tt)=0 V(la:ff)=1 .ic V(la:tt)=0 V(la:ff)=1