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Write-in-middle design.

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This commit is contained in:
Danila Fedorin 2021-03-14 23:11:00 -07:00
parent f289e84389
commit f3ffb39219
3 changed files with 26 additions and 13 deletions
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24
final/SRAM_bits.cir
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@ -145,18 +145,26 @@ Xn0 ot0 in0 ot1 eva nnd3 size ='size'
Xn1 ot1 in1 ot0 eva nnd3 size ='size' Xn1 ot1 in1 ot0 eva nnd3 size ='size'
.ends senseAmp .ends senseAmp
.subckt precharge charge rwtb clk diib
Xrdi rdi rwtb diib nnd2
Xnn chargeb clk rdi nnd2
Xout charge chargeb inv
.ends precharge
.subckt write1 btt bff dii rwt clk .subckt write1 btt bff dii rwt clk
* TODO: sizes * TODO: sizes
Xclk clkb clk inv size='25' Xclk clkb clk inv size='25'
Xdii diib dii inv size='25' Xdii diib dii inv size='25'
Xrwt rwtb rwt inv size='25'
Xrwn dorw clkb rwt nor2 size='50' Xrwn dorw clkb rwt nor2 size='50'
Xdt pdt dii gnd nn ww='50' Xdt pdt dii gnd nn ww='30'
Xdf pdf diib gnd nn ww='50' Xdf pdf diib gnd nn ww='30'
Xwt btt dorw pdt nn ww='50' Xwt btt dorw pdt nn ww='30'
Xwf bff dorw pdf nn ww='50' Xwf bff dorw pdf nn ww='30'
Xpct btt clk vdd pp ww='25' Xpcet pcet rwtb clk diib precharge
Xpcf bff clk vdd pp ww='25' Xpcef pcef rwtb clk dii precharge
Xpct btt clk vdd pp ww='10'
Xpcf bff clk vdd pp ww='10'
.ends write1 .ends write1
@ -181,8 +189,8 @@ Xh2 nn1 dot inv
.subckt readSub btt bff set rst rwt clk en .subckt readSub btt bff set rst rwt clk en
Xnd trigger rwt clk en nnd3 Xnd trigger rwt clk en nnd3
Xinv triggerb trigger inv Xinv triggerb trigger inv size='40'
Xamp set rst btt bff triggerb senseAmp size='200' Xamp set rst btt bff triggerb senseAmp size='40'
.ends read1 .ends read1
.subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3

10
final/testBuffer.cir
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@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel***** *********begin: topLevel*****
.param per = 3ns .param per = 1.15ns
.param dataLead=per*0.1 .param dataLead=per*0.1
.param lw=1800 .param lw=1800
.param wirew=12 .param wirew=12
@ -34,16 +34,16 @@ Xdii din dat1 period='per' start='per' total=4 duty=2
Xdec choose clk clk decModel Xdec choose clk clk decModel
Xwr bt1 bf1 din rdw clk write1 Xwr bt3 bf3 din rdw clk write1
Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew' Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=16 Xmd1 bt2 bf2 memLoad number=15
Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew' Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'
Xmd2 bt3 bf3 memLoad number=16 Xmd2 bt3 bf3 memLoad number=16
Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew' Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16 Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff memLoad number =15 Xmd4 btt bff memLoad number =16
Xla btt bff choose mem1 Xla bt1 bf1 clk mem1
Xrd btt bff set rst rdw clk choose readSub Xrd btt bff set rst rdw clk choose readSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect

5
final/todo.md Normal file
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@ -0,0 +1,5 @@
* [x] Figure out the weird opAmp behavior
* [ ] Design cell with strict metal policies
* [ ] Add precharger version of memory cell (or explain how they compose)
* [ ] Test cell in the _middle_.
* [ ] Walk through the consequences of the read/write block being in the middle.