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This commit is contained in:
Danila Fedorin 2021-03-14 21:13:43 -07:00
parent 5f8a49ab9a
commit f289e84389
2 changed files with 8 additions and 9 deletions
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4
final/SRAM_bits.cir
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@ -179,8 +179,8 @@ Xh1 dot nn1 inv
Xh2 nn1 dot inv
.ends read1
.subckt readSub btt bff set rst rwt clk
Xnd trigger rwt clk nnd2
.subckt readSub btt bff set rst rwt clk en
Xnd trigger rwt clk en nnd3
Xinv triggerb trigger inv
Xamp set rst btt bff triggerb senseAmp size='200'
.ends read1

13
final/testBuffer.cir
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@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel*****
.param per = 2ns
.param per = 3ns
.param dataLead=per*0.1
.param lw=1800
.param wirew=12
@ -31,7 +31,7 @@ vdd vdd 0 'supply'
Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50
Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1
Xdii din dat1 period='per' start='per' total=4 duty=2 sz=30
Xdec choose clk clk decModel
Xwr bt1 bf1 din rdw clk write1
@ -43,15 +43,14 @@ Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff memLoad number =15
Xla btt bff clk mem1
Xrd btt bff set rst rdw clk readSub
Xla btt bff choose mem1
Xrd btt bff set rst rdw clk choose readSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
.ic V(la:tt)=0 V(la:ff)=1
.ic V(bt2)=1
.tran 1p 'per*20'
.meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1