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Update with new wire model

This commit is contained in:
Danila Fedorin 2021-03-17 12:58:36 -07:00
parent 39ec744562
commit ff0edb93bb
1 changed files with 4 additions and 4 deletions
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8
final/SRAM_bits.cir
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@ -26,8 +26,8 @@
.subckt wire iot iof len=10 wid=10 .subckt wire iot iof len=10 wid=10
.param rr=0.8 .param rr=0.4
.param cc = '200e-15' .param cc = '100e-15'
rt iot iof 'rr*len*50/(wid)' rt iot iof 'rr*len*50/(wid)'
cf iof 0 'cc*len*wid*50/1e6' cf iof 0 'cc*len*wid*50/1e6'
@ -179,7 +179,7 @@ Xpct btt clk vdd pp ww='100'
Xpcf bff clk vdd pp ww='100' Xpcf bff clk vdd pp ww='100'
.ends write1 .ends write1
.subckt iWrite1 btt bff dii rwt clk .subckt iWrite1 btt bff dii rwt en clk
* TODO: sizes * TODO: sizes
Xclk clkb clk inv size='40' Xclk clkb clk inv size='40'
Xdii diib dii inv size='40' Xdii diib dii inv size='40'
@ -222,7 +222,7 @@ Xamp set rst btt bff triggerb senseAmp size='200'
.subckt iReadSub btt bff set rst rwt clk en .subckt iReadSub btt bff set rst rwt clk en
Xnd trigger rwt en clk nnd3 Xnd trigger rwt en clk nnd3
Xinv triggerb trigger inv size='40' Xinv triggerb trigger inv size='40'
Xamp set rst btt bff triggerb iSenseAmp size='40' Xamp set rst btt bff triggerb iSenseAmp size='120'
.ends read1 .ends read1
.subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3