62 lines
1.1 KiB
Plaintext
62 lines
1.1 KiB
Plaintext
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* File includes subcircuits and technology definitions
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.include ./SRAM_bits.cir
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*this cell emulates load from SRAM cells,
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* Number refers to the load from than number of cells
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.subckt memLoad ttt fff number=254
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Xnt ttt gnd dead nn ww='number*5'
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Xnf fff gnd dead nn ww='number*5'
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.ends memLoad
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*********begin: topLevel*****
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* Parameters
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.global gnd vdd
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.param gnd=0
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*********begin: topLevel*****
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.param per = 3n
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.param lw=5000
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.param wirew=3
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*DC supplies
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vdd vdd 0 'supply'
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Xclok clk dat1 period='per' start='per' total=1 duty=0.5 sz=120
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Xrdwr rdw dat1 period='per' start='per' total=2 duty=1
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Xdii dii dat1 period='per' start='per' total=3 duty=1
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* vary
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.param dip=0.05
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Vt bt2 0 PULSE('supply''supply-dip' 'per' 10p 10p '2*per' '4*per')
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Vf bf2 0 PULSE('supply-dip''supply' 'per' 10p 10p '2*per' '4*per')
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Xbit ad0 dat1 period='per' start='0.5*per' total=3 duty=1
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Xde ope ad0 clk decModel size=20
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* Xrd bt2 bf2 dot vdd clk read1
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Xrd bt2 bf2 set rst vdd clk readSub
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.ic v(dot)=0
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.tran 1p 50n
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