14 lines
668 B
Markdown
14 lines
668 B
Markdown
* [x] Figure out the weird opAmp behavior
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* [x] Design cell with strict metal policies
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* [x] Add precharger version of memory cell (or explain how they compose)
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* [x] Test cell in the _middle_.
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* [x] Walk through the consequences of the read/write block being in the middle.
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* [x] Figure out what to do with flopped write block.
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* [x] Test data close to write block (it pulls up past clock low!)
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* [ ] Drive wires to zero?
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* [x] Add missing well connection in layout
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* [x] Make sure width isn't too horrible
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* [ ] Model additional delay for read read/write block select?
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* [x] Model worst case of decoder
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* [x] Cite [this](https://ieeexplore.ieee.org/document/210039)
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