57 lines
1.2 KiB
Systemverilog
57 lines
1.2 KiB
Systemverilog
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module cpu_controller(input logic clk, reset,
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input logic [11:0] inputs,
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input logic spi_clk, spi_ss, spi_mosi,
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output logic [11:0] outputs);
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logic [31:0] inst;
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logic [7:0] addr;
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logic [19:0] the_void;
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logic prog;
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logic en;
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logic inst_ready;
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logic inst_done;
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logic inst_ready_edge;
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logic cpu_clk;
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edge_detector inst_ready_detector(
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.in(inst_ready),
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.clk(clk),
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.out(inst_ready_edge));
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logic prog_forward_clk;
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assign prog_forward_clk = inst_ready_edge & ~inst_done & prog;
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assign cpu_clk = reset | (en ? clk : prog_forward_clk);
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spi_slave prog_slave(
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.clk(clk),
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.reset(reset),
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.master_clk(spi_clk),
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.ss(spi_ss),
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.mosi(spi_mosi),
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.ready(inst_ready),
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.done(inst_done),
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.data(inst));
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cpu cpu_unit(
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.clk(cpu_clk),
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.inputs({4'b0, inputs}),
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.reset(reset),
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.prog(prog),
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.pinst(inst),
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.paddr(addr),
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.disp({the_void, outputs}));
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always_ff@(posedge clk)
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if (reset) begin
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prog <= 0;
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en <= 0;
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addr <= 0;
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end else begin
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en <= inst_done;
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prog <= (prog & ~inst_done) | (inst_ready_edge & (inst == 32'hCAFEBABE));
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addr <= addr + prog_forward_clk;
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end
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endmodule
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