Add the CPU controller.

cpu_controller.sv

@@ -0,0 +1,57 @@
+module cpu_controller(input logic clk, reset,
+					  input logic [11:0] inputs,
+					  input logic spi_clk, spi_ss, spi_mosi,
+					  output logic [11:0] outputs);
+	logic [31:0] inst;
+	logic [7:0] addr;
+	logic [19:0] the_void;
+	logic prog;
+	logic en;
+	
+	logic inst_ready;
+	logic inst_done;
+	logic inst_ready_edge;
+	
+	logic cpu_clk;
+	
+	edge_detector inst_ready_detector(
+		.in(inst_ready),
+		.clk(clk),
+		.out(inst_ready_edge));
+	
+	logic prog_forward_clk;
+	
+	assign prog_forward_clk = inst_ready_edge & ~inst_done & prog;
+	assign cpu_clk = reset | (en ? clk : prog_forward_clk);
+	
+	spi_slave prog_slave(
+		.clk(clk),
+		.reset(reset),
+		.master_clk(spi_clk),
+		.ss(spi_ss),
+		.mosi(spi_mosi),
+		.ready(inst_ready),
+		.done(inst_done),
+		.data(inst));
+		
+	cpu cpu_unit(
+		.clk(cpu_clk),
+		.inputs({4'b0, inputs}),
+		.reset(reset),
+		.prog(prog),
+		.pinst(inst),
+		.paddr(addr),
+		.disp({the_void, outputs}));
+		
+	always_ff@(posedge clk)
+		if (reset) begin
+			prog <= 0;
+			en <= 0;
+			addr <= 0;
+		end else begin
+			en <= inst_done;
+			prog <= (prog & ~inst_done) | (inst_ready_edge & (inst == 32'hCAFEBABE));
+			addr <= addr + prog_forward_clk;
+		end
+		
+endmodule

edge_detector.sv

@@ -0,0 +1,9 @@
+module edge_detector(input logic in, clk,
+					 output logic out);
+	logic old_in;
+	
+	always_ff@(posedge clk)
+		old_in <= in;
+	
+	assign out = in & ~old_in;
+endmodule

spi_slave.sv

@@ -0,0 +1,36 @@
+module spi_slave #(width=32)
+				  (input logic clk, reset,
+				   input logic master_clk, ss, mosi,
+				   output logic ready,
+				   output logic done,
+				   output logic [width-1:0] data);
+	logic [width-1:0] storage;
+	logic unsigned [$clog2(width)-1:0] counter;
+	logic old_clk;
+	
+	always_ff@(posedge clk)
+		if(reset) begin
+			counter <= 0;
+			old_clk <= 0;
+			storage <= 0;
+			done <= 0;
+			ready <= 0;
+		end else begin
+			if (~ss & master_clk & ~old_clk) begin
+				storage <= storage << 1 | mosi;
+				if (counter == width - 1) begin
+					ready <= 1;
+					done <= ~(|storage);
+					counter <= 0;
+				end else begin
+					done <= 0;
+					ready <= 0;
+					counter <= counter + 1;
+				end
+			end
+			old_clk <= master_clk;
+		end
+	
+	assign data = storage;
+	
+endmodule