36 lines
800 B
Systemverilog
36 lines
800 B
Systemverilog
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module spi_slave #(width=32)
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(input logic clk, reset,
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input logic master_clk, ss, mosi,
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output logic ready,
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output logic done,
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output logic [width-1:0] data);
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logic [width-1:0] storage;
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logic unsigned [$clog2(width)-1:0] counter;
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logic old_clk;
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always_ff@(posedge clk)
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if(reset) begin
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counter <= 0;
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old_clk <= 0;
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storage <= 0;
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done <= 0;
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ready <= 0;
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end else begin
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if (~ss & master_clk & ~old_clk) begin
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storage <= storage << 1 | mosi;
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if (counter == width - 1) begin
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ready <= 1;
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done <= ~(|storage);
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counter <= 0;
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end else begin
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done <= 0;
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ready <= 0;
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counter <= counter + 1;
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end
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end
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old_clk <= master_clk;
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end
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assign data = storage;
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endmodule
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