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edge_detector.sv

@@ -1,9 +1,14 @@
+/**
+ * Simple edge detector circuit. Takes in a clock and a signal,
+ * and produces an output of 1 when the signal changes from 0 to 1.
+ * Otherwise, the output is 0.
+ */
 module edge_detector(input logic in, clk,
 					 output logic out);
 	logic old_in;
-	
+
 	always_ff@(posedge clk)
 		old_in <= in;
-	
+
 	assign out = in & ~old_in;
-endmodule
+endmodule