15 lines
348 B
Systemverilog
15 lines
348 B
Systemverilog
/**
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* Simple edge detector circuit. Takes in a clock and a signal,
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* and produces an output of 1 when the signal changes from 0 to 1.
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* Otherwise, the output is 0.
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*/
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module edge_detector(input logic in, clk,
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output logic out);
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logic old_in;
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always_ff@(posedge clk)
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old_in <= in;
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assign out = in & ~old_in;
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endmodule
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