ECE-271/VerilogCPU
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A CPU written in SystemVerilog for ECE 271.
3 Commits 1 Branch 0 Tags 212 KiB
SystemVerilog 51.8%
Crystal 48.2%
351b23b0f7
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Danila Fedorin 351b23b0f7 Add the basic fibonacci sequence program.
2018-06-05 17:25:12 -07:00
tasm Add the basic fibonacci sequence program. 2018-06-05 17:25:12 -07:00
alu.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
assembler.cr Write basic assembler. 2018-06-05 17:24:31 -07:00
cpu.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
memory.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
mux2.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
mux4.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00
register.sv Initial commit. Working CPU! 2018-06-05 00:06:45 -07:00