VerilogCPU/edge_detector.sv

/**
 * Simple edge detector circuit. Takes in a clock and a signal,
 * and produces an output of 1 when the signal changes from 0 to 1.
 * Otherwise, the output is 0.
 */
module edge_detector(input logic in, clk,
					 output logic out);
	logic old_in;

	always_ff@(posedge clk)
		old_in <= in;

	assign out = in & ~old_in;
endmodule