17 lines
393 B
Systemverilog
17 lines
393 B
Systemverilog
module memory #(width=32)
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(input logic [7:0] raddr, waddr,
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input logic [width-1:0] in,
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input logic clk, wen, reset,
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output logic [width-1:0] out);
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logic [width-1:0] data [0:255];
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always_ff@(posedge clk)
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if(reset) begin
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data <= '{default: 0};
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end else begin
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if(wen) begin
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data[waddr] <= in;
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end
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end
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assign out = data[raddr];
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endmodule |