Fix a port width problem, and change file permissions.
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parent
d183a7e1de
commit
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2
cpu.sv
2
cpu.sv
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@ -75,7 +75,7 @@ module cpu (input logic clk, reset,
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assign pc_compute = rt_val + const_val;
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mux2 #(8) pc_mux(
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.left(pc + 1),
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.left(pc + 8'b01),
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.right(pc_compute),
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.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
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.out(pc_next));
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4
memory.sv
Executable file → Normal file
4
memory.sv
Executable file → Normal file
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@ -8,7 +8,9 @@ module memory #(width=32)
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if(reset) begin
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data <= '{default: 0};
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end else begin
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if(wen) data[waddr] <= in;
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if(wen) begin
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data[waddr] <= in;
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end
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end
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assign out = data[raddr];
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0
register.sv
Executable file → Normal file
0
register.sv
Executable file → Normal file
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