18 lines
431 B
Systemverilog
18 lines
431 B
Systemverilog
module registers #(width=32)
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(input logic [2:0] raddr1, raddr2, waddr,
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input clk, wen, reset,
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input logic [width-1:0] in,
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output logic [width-1:0] out1, out2);
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logic [width-1:0] data [0:7];
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always_ff@(posedge clk)
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if (reset) begin
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data <= '{default: 0};
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end else begin
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if(wen) data[waddr] <= in;
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end
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assign out1 = data[raddr1];
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assign out2 = data[raddr2];
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endmodule |