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\title{Homework 1}
The three version of Moore's Law are as follows:
\item \textbf{Scaling Up}. We were able to shrink the size
of a transistor, thereby roughly doubling the number of transistors
on a single chip every 1-2 years.
\item \textbf{Scaling Down}. The costs of a single
transistor decreased by about 30\% every year.
This made it cost-effective to use microprocessors
for various applications.
\item \textbf{Scaling Out}. We are able to combine
microprocessors with other technologies, even
entirely in our silicon processing. For instance,
we can make tiny accelerometers, or use a saphire
substrate instead of silicon to work with
According to Denard scaling, power density remains constant.
If this holds, we can scale down our designs and things
will continue to just work.
We were not able to scale voltage at the desired factor. Eventually,
thermally-induced voltages are comparable in magnitude with the voltages
we use to drive our transistors, which makes them work unreliably or leak
charge. Because we can no longer scale voltage down, our power density
keeps growing. This means that our processors get increasingly hot,
which, in turn, limits the clock speeds of our designs.
A wafer is first covered in Photoresist, a chemical that is
either soluble until or before it comes into contact with UV light.
UV light is shined onto the photoresist past a mask, which creates
regions that are exposed to UV (where not blocked by the mask) and regions
that are in ``shadow'' (blocked by the mask). Depending on the type of
photoresist, one of the regions (but not the other) becomes soluble,
and can be removed using a solvent (developer). This leaves a pattern
of photoresist on top of the wafer. Different approaches can then
be used that affect only the areas not covered by photoresist (for instance,
if gold is below the photoresist layer, a chemical can be used to
dissolve the gold; the chemical will not touch the gold covered by
photoresist, thus leaving it in place).
Not quite sure what this question means, but I have a few thoughts:
\item Instead of trying to reduce the wavelength of light further
down (which didn't actually work out), we use the same old
193nm light, and focused on refining the technique.
\item We started to perform multiple lithography (and maybe etch)
steps for a single layer, which made it possible to
halve (or further reduce) the minimum pitch. Exposing
photoresist more than once also made it possible (from what I can tell) to use all the special
techniques (off-axis illumination, immersion, RET), which otherwise constrain masks to being only
horizontal or only vertical.
\item Self-aligned mutli-patterning techniques cannot really lay down
``holes'' in lines; these holes have to be added later.
As a result, layouts of modern CPUs are very regular,
since many components ``share'' a single line. This
allows for far less freedom in where to place the
various components of a chip.
From the ``Rosetta Stone of Lithography'' it looks like with true double patterning,
the smallest we can get is the 10nm node (50nm pitch).
However, the Breakfast Bytes article, right after saying 50nm is the smallest
pitch we can get with double patterning, brings up SADP, which is also
double patterning, but can go as low as 40nm. In the Rosetta Stone,
however, 40nm seems to correspond to `Higher-order pitch division', and not
double patterning, so I still think 50nm pitch / 10nm node is the answer here.
We use tin plasma! Apparently, tin is ``fairly efficient'' at converting laser
light into EUV.