Labs/final/testBuffer.cir

* File includes subcircuits and technology definitions
.include ./SRAM_bits.cir


*this cell emulates load from SRAM cells,
* Number refers to the load from than number of cells
.subckt memLoad ttt fff number=254
Xnt ttt gnd dead nn ww='number*5'
Xnf fff gnd dead nn ww='number*5'
.ends memLoad



*********begin: topLevel*****

* Parameters
.global gnd vdd
.param gnd=0


*********begin: topLevel*****
.param per = 3ns
.param dataLead=per*0.1
.param lw=1800
.param wirew=12

vdd vdd 0 'supply'

Xclok clk               dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50
Xrdwr rdw               dat1 period='per' start='2*per'        total=2 duty=1
Xdii din                dat1 period='per' start='per'          total=4 duty=2   sz=30
Xdec choose clk clk decModel


Xwr bt1 bf1 din rdw clk write1
Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=16
Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'
Xmd2 bt3 bf3 memLoad number=16
Xw3 bt3 bt4 bf3 bf4  clk   wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff  clk   wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff             memLoad number =15
Xla btt bff choose         mem1
Xrd btt bff set rst rdw clk choose readSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect

.ic V(la:tt)=0 V(la:ff)=1
.ic V(bt2)=1
.tran 1p 'per*20'
.meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1