Add the CPU controller.

edge_detector.sv

@@ -0,0 +1,9 @@
+module edge_detector(input logic in, clk,
+					 output logic out);
+	logic old_in;
+	
+	always_ff@(posedge clk)
+		old_in <= in;
+	
+	assign out = in & ~old_in;
+endmodule