Fix a port width problem, and change file permissions.

This commit is contained in:
Danila Fedorin 2018-06-05 22:56:46 -07:00
parent d183a7e1de
commit bfe4b65788
5 changed files with 4 additions and 2 deletions

2
cpu.sv
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@ -75,7 +75,7 @@ module cpu (input logic clk, reset,
assign pc_compute = rt_val + const_val; assign pc_compute = rt_val + const_val;
mux2 #(8) pc_mux( mux2 #(8) pc_mux(
.left(pc + 1), .left(pc + 8'b01),
.right(pc_compute), .right(pc_compute),
.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))), .select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
.out(pc_next)); .out(pc_next));

4
memory.sv Executable file → Normal file
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@ -8,7 +8,9 @@ module memory #(width=32)
if(reset) begin if(reset) begin
data <= '{default: 0}; data <= '{default: 0};
end else begin end else begin
if(wen) data[waddr] <= in; if(wen) begin
data[waddr] <= in;
end
end end
assign out = data[raddr]; assign out = data[raddr];

0
mux2.sv Executable file → Normal file
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0
mux4.sv Executable file → Normal file
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0
register.sv Executable file → Normal file
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