Labs/final/testBuffer.cir

* File includes subcircuits and technology definitions
.include ./SRAM_bits.cir


*this cell emulates load from SRAM cells,
* Number refers to the load from than number of cells
.subckt memLoad ttt fff number=254
Xnt ttt gnd dead nn ww='number*5'
Xnf fff gnd dead nn ww='number*5'
.ends memLoad



*********begin: topLevel*****

* Parameters
.global gnd vdd
.param gnd=0


*********begin: topLevel*****
.param per = 1.9ns
.param dataLead=per*0.1
.param lw=2200
.param wirew=12

vdd vdd 0 'supply'

Xclok clk               dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
Xad ad               dat1 period='per' start='per' total=1 duty=0.5 sz=300
Xrdwr rdw               dat1 period='per' start='2*per'        total=2 duty=1 sz=300
Xdii din                dat1 period='per' start='per'          total=4 duty=2 sz=300

Xinv1 clkb1 clk inv
Xinv2 clkb2 clkb1 inv
Xinv3 clkb3 clkb2 inv
Xinv4 clkb4 clkb3 inv size='300'
Xinv5 clkb5 clkb4 inv
Xinv6 clkb6 clkb5 inv size='300'

Xad adf ad clk flop
Xdinff dinf din clk flop
Xrdwff rdwf rdw clk flop
Xrotff dotf dot clk flop
Xdec choose adf clk decModel

Xwr bt3 bf3 dinf rdwf clkb6 iWrite1
Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=15
Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'
Xmd2 bt3 bf3 memLoad number=16
Xw3 bt3 bt4 bf3 bf4  clk   wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff  clk   wire_precharge len='lw/4' wid='wirew'
Xmd4 bt3 bf3             memLoad number =16
* Xla bt1 bf1 choose         mem1
* Xla bt3 bf3 choose         mem1
Xla btt bff choose         mem1
Xrd btt bff set rst rdwf clk choose iReadSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect

.ic V(la:tt)=0 V(la:ff)=1
.ic V(bt2)=1
.tran 1p 'per*20'
.meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1