Add comments.

alu.sv

@@ -1,3 +1,19 @@
+/**
+ * Arithmetic Logic Unit, as described in our book. This is a general
+ * purpose aritmetic circuit. The width parameter specifies the operand width,
+ * and left and right are the operands. op is the instruction, which decodes as
+ * follows:
+ 
+ * 000 left AND right
+ * 001 left OR right
+ * 010 left + right
+ * 011 unused
+ * 000 left AND NOT right
+ * 001 left OR NOT right
+ * 010 left - right
+ * 011 SLT left, right
+ *
+ */
 module alu #(width=32)
 			 (input logic [width-1:0] left, right,
 			  input logic [2:0] op,

cpu.sv

@@ -1,3 +1,11 @@
+/**
+ * Programmable CPU to run arbitrary assembly.
+ * clk, reset parameters behave as expected.
+ * inputs are data from the outside world, that are read via CPU instruction.
+ * prog, pinst, and paddr are all used to program the CPU:
+ * - prog is a flag. When high, instead of executing, it writes instructions to memory.
+ * - paddr is the address at which instructions are inserted.
+ */
 module cpu 	(input logic clk, reset,
 			 input logic prog,
 			 input logic [15:0] inputs,

cpu_controller.sv

@@ -1,3 +1,11 @@
+/**
+ * Controller to interface CPU with the outside world.
+ * The clk and reset inputs work as expected.
+ * Inputs are fed in from the various input sources,
+ * and given directly to CPU.
+ * spi_clk, spi_ss and spi_mosi are SPI connections used to program the CPU.
+ * Outputs displayed from the CPU disp instruction.
+ */
 module cpu_controller(input logic clk, reset,
 					  input logic [11:0] inputs,
 					  input logic spi_clk, spi_ss, spi_mosi,

edge_detector.sv

@@ -1,3 +1,8 @@
+/**
+ * Simple edge detector circuit. Takes in a clock and a signal,
+ * and produces an output of 1 when the signal changes from 0 to 1.
+ * Otherwise, the output is 0.
+ */
 module edge_detector(input logic in, clk,
 					 output logic out);
 	logic old_in;

memory.sv

@@ -1,3 +1,9 @@
+/**
+ * CPU-specific memory. raddr is used for reading,
+ * while wen (write enable), waddr, and in are used in combination to write.
+ * Reads are performed immediately, but writes are performed on
+ * positive clock edge. Reset clears the memory to 0.
+ */
 module memory #(width=32)
 				(input logic [7:0] raddr, waddr,
 				 input logic [width-1:0] in,

mux2.sv

@@ -1,3 +1,5 @@
+/* A two-input multiplexer.
+ */
 module mux2 #(width=32)
 			 (input logic [width-1:0] left, right,
 			  input logic select,

mux4.sv

@@ -1,3 +1,6 @@
+/**
+ * A four-input multiplexer.
+ */
 module mux4 #(width=32)
 			 (input logic [width-1:0] first, second, third, fourth,
 			  input logic [1:0] select,

register.sv

@@ -1,3 +1,9 @@
+/**
+ * Register file as used by the CPU. Has two read addresses so that
+ * two-register instructions can be performed in one cycle. Just like memory,
+ * reading is asynchronous, while writes occur on positive clock edge.
+ * wen, waddr, and in are used to write to register memory.
+ */
 module registers #(width=32)
 				   (input logic [2:0] raddr1, raddr2, waddr,
 				    input clk, wen, reset,

spi_slave.sv

@@ -1,3 +1,14 @@
+/**
+ * Specialized SPI slave.
+ * Reads width bits at a time, and sets the ready flag
+ * whenever a full 32 bits has been read. Also, recognizes
+ * 0x00 as a pattern, and when full 0s are read, sets the done flag.
+ * 0x00 is a special value in the CPU programming process that indicates
+ * end-of-program.
+ *
+ * master_clk, ss, and mosi are all SPI-specific inputs.
+ * data should only be read when ready is high.
+ */
 module spi_slave #(width=32)
 				  (input logic clk, reset,
 				   input logic master_clk, ss, mosi,