Fix a port width problem, and change file permissions.

2018-06-05 22:56:46 -07:00
parent d183a7e1de
commit bfe4b65788
5 changed files with 4 additions and 2 deletions
--- a/cpu.sv
+++ b/cpu.sv
@@ -75,7 +75,7 @@ module cpu 	(input logic clk, reset,
 	assign pc_compute = rt_val + const_val;

 	mux2 #(8) pc_mux(
-		.left(pc + 1),
+		.left(pc + 8'b01),
 		.right(pc_compute),
 		.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
 		.out(pc_next));