Fix a port width problem, and change file permissions.

memory.sv

@@ -8,7 +8,9 @@ module memory #(width=32)
 		if(reset) begin
 			data <= '{default: 0};
 		end else begin
-			if(wen) data[waddr] <= in;
+			if(wen) begin 
+				data[waddr] <= in;
+			end
 		end
 	
 	assign out = data[raddr];