Fix a port width problem, and change file permissions.

cpu.sv

@@ -75,7 +75,7 @@ module cpu 	(input logic clk, reset,
 	assign pc_compute = rt_val + const_val;
 
 	mux2 #(8) pc_mux(
-		.left(pc + 1),
+		.left(pc + 8'b01),
 		.right(pc_compute),
 		.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
 		.out(pc_next));

memory.sv

@@ -8,7 +8,9 @@ module memory #(width=32)
 		if(reset) begin
 			data <= '{default: 0};
 		end else begin
-			if(wen) data[waddr] <= in;
+			if(wen) begin 
+				data[waddr] <= in;
+			end
 		end
 	
 	assign out = data[raddr];