|
|
12856ef152
|
Use improved senseamp to strengthen performance.
|
2021-03-16 14:28:24 -07:00 |
|
|
|
ca72f3eb3d
|
Rollback to 1.3ns and no write flops.
|
2021-03-16 12:22:50 -07:00 |
|
|
|
e5b0166d8c
|
With flip flops.
|
2021-03-15 22:24:43 -07:00 |
|
|
|
8ba9d02a8e
|
1.24ns
|
2021-03-15 16:02:04 -07:00 |
|
|
|
c866f63e8c
|
1.3 nanoseconds
|
2021-03-15 15:17:04 -07:00 |
|
|
|
f3ffb39219
|
Write-in-middle design.
|
2021-03-14 23:11:00 -07:00 |
|
|
|
f289e84389
|
Current best effort.
|
2021-03-14 21:13:43 -07:00 |
|
|
|
5f8a49ab9a
|
WIP (still buggy) 2ns design
|
2021-03-12 13:53:24 -08:00 |
|
|
|
2010fcdf52
|
Add initial version of SRAM design.
|
2021-03-09 19:15:39 -08:00 |
|
|
|
8285087e3f
|
Add Scott's various test files.
|
2021-03-09 19:15:28 -08:00 |
|
|
|
b58f4df33e
|
Add my initial definitions of SRAM bits.
|
2021-03-09 19:15:07 -08:00 |
|
|
|
cf73ec9016
|
Add lab 3 sources.
|
2021-01-27 15:05:45 -08:00 |
|
|
|
a55e55f04f
|
Update process script to generate TeX.
|
2021-01-27 15:04:23 -08:00 |
|
|
|
1ca79fc52b
|
Update processing script.
|
2021-01-18 13:56:27 -08:00 |
|
|
|
b32dfd2a36
|
Add required Python packages to git.
|
2021-01-14 20:00:08 -08:00 |
|
|
|
a548f96a95
|
Add libe writeup and delete useless inages.
|
2021-01-14 19:59:13 -08:00 |
|
|
|
5ce4719a1b
|
Avoid re-running ltspice
|
2021-01-14 19:57:37 -08:00 |
|
|
|
61b22fffdf
|
Add lab 2 parameters and simulation script.
|
2021-01-14 19:54:02 -08:00 |
|
|
|
b41e616236
|
Update lab image.
|
2021-01-12 22:19:26 -08:00 |
|
|
|
2787981efc
|
Add initial drawings of cross section
|
2021-01-12 14:25:03 -08:00 |
|
