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• f317a7e8da Add some minor additional sections to report. master Danila Fedorin 2021-03-17 13:34:04 -0700
• 90a5aed6ec Size sense amp back to 40 Danila Fedorin 2021-03-17 13:12:55 -0700
• c6d7795074 Update report with new performance characteristics. Danila Fedorin 2021-03-17 13:09:15 -0700
• d8f4a272e3 Update to use new wire model's characteristics. Danila Fedorin 2021-03-17 13:07:33 -0700
• ff0edb93bb Update with new wire model Danila Fedorin 2021-03-17 12:58:36 -0700
• 39ec744562 Update report. Danila Fedorin 2021-03-17 12:21:35 -0700
• 6530e7ef8c 1.9ns everywhere. Danila Fedorin 2021-03-17 12:19:33 -0700
• 71195df7c9 Add final SRAM design. Danila Fedorin 2021-03-17 12:19:17 -0700
• 0c1d8611b1 Add missing images. Danila Fedorin 2021-03-17 12:19:02 -0700
• b99403a4ff Update TODOs. Danila Fedorin 2021-03-17 12:16:02 -0700
• 9afa839bff Add TODO. Danila Fedorin 2021-03-17 11:51:50 -0700
• 6f99879b8f Update electric files. Danila Fedorin 2021-03-17 09:00:29 -0700
• fe52f689f9 Upload files to 'final' Danila Fedorin 2021-03-17 00:32:18 -0700
• c171b0374b Upload files to 'final' Danila Fedorin 2021-03-17 00:02:13 -0700
• eb8d068519 Update 'final/todo.md' Danila Fedorin 2021-03-17 00:00:34 -0700
• 6db76f4fd3 Update todo Danila Fedorin 2021-03-16 23:25:36 -0700
• 64ee80be63 Update report. Danila Fedorin 2021-03-16 23:25:30 -0700
• 6b963c967b Merge branch 'master' of dev.danilafe.com:ECE-571/Labs Danila Fedorin 2021-03-16 19:02:58 -0700
• 4d4ceddcc6 Update todos Danila Fedorin 2021-03-16 19:02:06 -0700
• 75381749d7 Add initial designs. Danila Fedorin 2021-03-16 18:32:56 -0700
• d2f53a9a4f Update 'final/todo.md' Danila Fedorin 2021-03-16 18:19:45 -0700
• 0f6426958e Update 'final/todo.md' Danila Fedorin 2021-03-16 16:47:53 -0700
• 8b9eabdec1 1.33ns with flip flops and bug mitigation Danila Fedorin 2021-03-16 16:30:28 -0700
• e077bb9071 1.35ns with flip flops and bug mitigation Danila Fedorin 2021-03-16 16:20:35 -0700
• 76899cb8a3 2ns with flops. Danila Fedorin 2021-03-16 15:44:09 -0700
• 12856ef152 Use improved senseamp to strengthen performance. Danila Fedorin 2021-03-16 14:28:24 -0700
• ca72f3eb3d Rollback to 1.3ns and no write flops. Danila Fedorin 2021-03-16 12:22:50 -0700
• e5b0166d8c With flip flops. Danila Fedorin 2021-03-15 22:24:43 -0700
• 8ba9d02a8e 1.24ns Danila Fedorin 2021-03-15 16:02:04 -0700
• c866f63e8c 1.3 nanoseconds Danila Fedorin 2021-03-15 15:17:04 -0700
• f3ffb39219 Write-in-middle design. Danila Fedorin 2021-03-14 23:11:00 -0700
• f289e84389 Current best effort. Danila Fedorin 2021-03-14 21:13:43 -0700
• 5f8a49ab9a WIP (still buggy) 2ns design Danila Fedorin 2021-03-12 13:53:24 -0800
• 2010fcdf52 Add initial version of SRAM design. Danila Fedorin 2021-03-09 19:15:39 -0800
• 8285087e3f Add Scott's various test files. Danila Fedorin 2021-03-09 19:15:28 -0800
• b58f4df33e Add my initial definitions of SRAM bits. Danila Fedorin 2021-03-09 19:15:07 -0800
• cf73ec9016 Add lab 3 sources. Danila Fedorin 2021-01-27 15:05:45 -0800
• a55e55f04f Update process script to generate TeX. Danila Fedorin 2021-01-27 15:04:23 -0800
• 1ca79fc52b Update processing script. Danila Fedorin 2021-01-18 13:56:27 -0800
• b32dfd2a36 Add required Python packages to git. Danila Fedorin 2021-01-14 20:00:08 -0800
• a548f96a95 Add libe writeup and delete useless inages. Danila Fedorin 2021-01-14 19:59:13 -0800
• 5ce4719a1b Avoid re-running ltspice Danila Fedorin 2021-01-14 19:57:37 -0800
• 61b22fffdf Add lab 2 parameters and simulation script. Danila Fedorin 2021-01-14 19:54:02 -0800
• b41e616236 Update lab image. Danila Fedorin 2021-01-12 22:19:26 -0800
• 2787981efc Add initial drawings of cross section Danila Fedorin 2021-01-12 14:25:03 -0800