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4d4ceddcc6
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Update todos
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2021-03-16 19:02:06 -07:00 |
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8b9eabdec1
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1.33ns with flip flops and bug mitigation
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2021-03-16 16:30:28 -07:00 |
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e077bb9071
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1.35ns with flip flops and bug mitigation
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2021-03-16 16:20:35 -07:00 |
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76899cb8a3
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2ns with flops.
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2021-03-16 15:44:09 -07:00 |
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12856ef152
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Use improved senseamp to strengthen performance.
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2021-03-16 14:28:24 -07:00 |
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ca72f3eb3d
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Rollback to 1.3ns and no write flops.
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2021-03-16 12:22:50 -07:00 |
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e5b0166d8c
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With flip flops.
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2021-03-15 22:24:43 -07:00 |
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8ba9d02a8e
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1.24ns
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2021-03-15 16:02:04 -07:00 |
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c866f63e8c
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1.3 nanoseconds
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2021-03-15 15:17:04 -07:00 |
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f3ffb39219
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Write-in-middle design.
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2021-03-14 23:11:00 -07:00 |
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f289e84389
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Current best effort.
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2021-03-14 21:13:43 -07:00 |
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5f8a49ab9a
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WIP (still buggy) 2ns design
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2021-03-12 13:53:24 -08:00 |
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2010fcdf52
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Add initial version of SRAM design.
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2021-03-09 19:15:39 -08:00 |
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8285087e3f
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Add Scott's various test files.
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2021-03-09 19:15:28 -08:00 |
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b58f4df33e
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Add my initial definitions of SRAM bits.
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2021-03-09 19:15:07 -08:00 |
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